In a conventional process of forming a mask for a design layer of an integrated circuit (IC) having M original design features and N original dummy features, an OPC (Optical Proximity Correction) program is typically run on characteristic data sets of the M original design features, resulting in OPC-applied characteristic data sets of M OPC-applied design features. Next, the mask is formed from the OPC-applied characteristic data sets of the M OPC-applied design features, and the N dummy features. The next generation technologies will require OPC-applied dummy features as well, due to shrinking size of the dummy features. One simple procedure is to run an OPC program on the M original design features and the N original dummy features, resulting in OPC-applied mask of M OPC-applied design features and N OPC-applied dummy features. However, the numbers M and N are usually very large, and therefore, running an OPC program on both original design features and original dummy features together consumes a large amount of computational resources and time, and would not be a viable solution.
Design-fill shapes (or dummy features, used interchangeably herein) are used to fill empty spaces in IC design layouts in order to aid in formation of physical ICs from those layouts, e.g., in order to provide object density when a polishing process (e.g., chemical mechanical polishing, or CMP) is performed on a particular layer. It may be desirable to use design-fill shapes that match or nearly match design shapes from an OPC library in order to meet the process tolerance (e.g., CMP uniformity) requirements of next generation technologies. However, it may also be desirable to utilize design-fill shapes that have few polygon edges in order to reduce the time required to form masks which ultimately outline those shapes. Conventional approaches for forming design-fill shapes include iteratively and manually modifying OPC library shapes, using a rule based modification of design-fill shapes and/or removing edges after running OPC on the layout. These approaches can be time-consuming and inaccurate.